Metal oxide thin film transistors (MOTET) are gaining interest as high performance TFT backplanes for large area applications such as active matrix organic light emitting diodes (AMOLED). MOTFTs have gained popularity because of their high mobility in amorphous and/or nano-crystalline states and low fabrication temperature. The high mobility enables applications that require high performance such as integrated drivers, driving OLED displays. See for example the U.S. Pat. No. 7,977,868 entitled “Active Matrix Light Emitting Display”, and incorporated herein by reference. The amorphous and/or nano-crystalline nature enables short range uniformity which plagues poly-Si TFTs. The low fabrication temperature makes the MOTFTs attractive for large area flat panel displays (FPD) because they can be fabricated on low cost substrates and even achieve flexible FPDs.
Some remaining challenges are to reduce the parasitic gate-to-source and gate-to-drain capacitances. These capacitances become important with display frame rate, when the number of pixels in a row increase along with information content. Overlap between the gate and the source/drain regions leads to the parasitic gate-to-source and gate-to-drain capacitances. The overlap is necessary to insure that the channel is fully controlled by the gate. But an excessive overlap leads to the large parasitic capacitances. The degree of overlapping is determined by the alignment capability between the patterning of the gate layer, the channel layer, and the source/drain metal layer. There will be some degree of misalignment due to tool capability, which can also be eliminated by the present method. The other major misalignment, and that which is also addressed here, is due to substrate deformation (i.e. deformation of substrates in processing such as in glass substrates due to high temperature treatment or in plastic substrates due to an increase in moisture, chemical and heat treatment). Basically, the overlap is designed so that under the worst circumstance there will be overlap between the gate and the source/drain metal. For low cost FPDs the area of the substrates is large and the size of exposure field is also large. The misalignment is going to be relatively large over large substrates and thus large exposure fields. Large overlap designs are needed to compensate for all potential misalignments, thereby leading to large parasitic overlap capacitances.
Typically, misalignment due to deformation increases with the size of the exposure field. One way to compensate for the deformation is to reduce the exposure field by performing multiple exposures on the substrate and then stitching the multiple patterns together. However, this approach substantially increases the manufacturing cost due to lower through put and the high cost of stitching. Many of the large area applications use either glass or plastic substrates. To produce TFTs on large areas at low cost, it is advantageous to use low cost lithographic tools such as proximity/projection aligners/scanners rather than the more expensive stepper tools.
The large parasitic capacitances lead to slower waveforms (and thus limited number of pixels for a given frame time) and more power consumption. It is important therefore to reduce the parasitic capacitances while maintaining the minimum overlap between the gate and the source/drain to ensure that the channel is fully controlled by the gate. Also, these conditions have to be met over the large substrate areas regardless of substrate deformations and tool alignment capabilities.
Another item to be addressed herein is the cost of manufacturing the TFTs. Primarily, the cost of manufacturing TFTs depends on the number of masks used during the manufacturing process. Lithography is a big part of the fabrication cost. Therefore, a reduction in the number of masks (e.g. from four masks to three masks), while still achieving the self-alignment between the gate and the source/drain, or between the gate and the etch-stop, or between the S/D electrodes and the pixel electrode pad, can result in a major reduction in the overall cost.
It would be highly advantageous to have a self-aligned process in which there are no or fewer critical alignment steps.
Accordingly, it is an object of the present invention to provide new and improved methods of fabricating self-aligned metal oxide TFTs and thin film backpanel circuit.
It is another object of the present invention to provide new and improved methods of fabricating metal oxide TFTs and thin film backpanel circuit including no critical alignment tools or steps and using a minimum of process steps.
It is another object of the present invention to provide new and improved methods of fabricating self-aligned metal oxide TFTs and thin film backpanel circuit using a reduced number of masks.
It is another object of the present invention to provide new and improved methods of fabricating self-aligned metal oxide TFTs and thin film backpanel circuit with reduced inter-electrode capacitance.
It is another object of the present invention to provide a new and improved metal oxide TFT and thin film backpanel circuit with reduced inter-electrode capacitance.
It is another object of the present invention to provide a new and improved metal oxide TFT and thin film backpanel circuit with reduced alignment error and thus smaller channel length.
It is another object of the present invention to provide a new and improved method of making display backpanels with self-aligned metal oxide TFT with reduced inter-electrode capacitance.
It is another object of the present invention to provide a method of making high uniformity over large display area with phototools with low alignment accuracy.